Honored Contributor
Honored Contributorwuz73, clock tree delays are never 0, even with a PLL, and they don't account for output buffers, whcih are generally pretty big. You could shift your clock back in time 1ns(and add a multicycle -setup 2), so that your setup requirement goes from 5ns to 6ns(and you'd have a 1ns hold requirement.)
Note that you're doing a 200MHz I/O interface. Those speeds are where you start having to do things source synchronously, although it's kind of at the edge. (Also, what I/O standard is it. Things like LVDS are often used here, but of course that uses two pins...)
