Output_Pin tming not met in TimeQuest.

I'm having a similar problem, except that I have PLL and I think I have constrained everything correctly. Here's my timing report:

Data Arrival Path
Total Incr  Type  Element
----- ----- ---- --------
0.000 0.000       launch edge time
0.326 0.326       clock network delay
0.558 0.232 uTco  out~reg0
0.558 0.000 CELL  out~reg0|q
2.203 1.645 IC    out~output|i
4.355 2.152 CELL  out~output|o
4.355 0.000 CELL  out
Data Required Path
Total  Incr  Type Element
----- ------ ---- ---------
5.000  5.000      latch edge time
5.000  0.000      clock network delay
4.910 -0.090      clock uncertainty
3.410 -1.500 oExt out

As you can see, I have "set_output_delay 1 [get_ports out] -clock clk", and clk has been compensated with PLL. However, there's still non-zero clock tree delay and the IOOBUF has a really big delay.

What can I do to close the output timing? Note that I need ~1ns improvement. So even if the clock tree has 0ns insertion delay it won't help.