Forum Discussion
Altera_Forum
Honored Contributor
16 years agoOne followup to Daixiwen's comment. This is actually a very loose requirement, probably impossibly loose. All it says is that the external board and device chew up 100ps of the data period. set_output_delay is not a requirement on what the FPGA has to meet, but saying what the external devices have already met, and the FPGA's requirements are based on that. For example, the clock period seems to be 5ns. The external -max delay is 200ps, so that means the FPGA has 4.8ns of that clock period to work with. Yes, 4.8ns can be tight to get a signal out in, but still, the whole data period is being given to the FPGA, not the external device. (I think the poster said those numbers could/would be changed..)