Honored Contributor
Honored ContributorWhat's $rd_clk? You have a clock delay of -3.452ns on the latching clock. Since your requirement was originally 5ns, and taking 3.452ns off, you're really asking for an extremely tight requirement.
I'm guessing the -3.452ns is wrong. Note that your -clock option should generally be a virtual clock(i.e. it's not applied to anything physical on the FPGA). Something like: create_clock -name rd_clk_ext -period 5.0 set_output_delay -clock rd_clk_ext There are a number of other posts about this, but hopefully that helps. (I'm not sure if your source clock is correct either, with a delay of 0.14. I would run the report_timing command with the option -detail full_path, and then make sure it traces all the way back to the input clock port.)
