Output pin load assignment

I just glanced at the AN 366 suggestion, but it looks like a good reference.

This part of the help page for "Output Pin Load logic option" is relevant to your question. Any board trace capacitance that affects the rise/fall time of the signal as seen at the receiver needs to be included.

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The value entered for the output pin load should be the loading value for the board trace capacitance and target load capacitance. The Altera device pin/package capacitance is already factored in the output pin load value.

. . .

The following equation is used to determine the changes in the output delay and depends on the Output Pin Load option:

output_delay = default_output_delay + ((output_load - default_output_load) * derating factor)

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See the help page for the derating factors. I got to the help page by pressing "F1" while I had an Output Pin Load assignment selected in the Assignment Editor.

The Assignment Editor Information pane has this:

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Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. Note: These settings affect FPGA pins only. To specify board trace, termination, and capacitive load parameters for use with Advanced I/O Timing, use the Board Trace Model tab. Capacitive loading is ignored if applied to anything other than an output or bidirectional pin, or if Advanced I/O Timing is enabled.

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AN 366 is dated July 2006, and Advanced I/O Timing is fairly new. The Quartus handbook has information about Advanced I/O Timing.