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Maybe it can be improved, but at least I can make it fit in the CPLD since a reduction of ~16% than using the classic "variable <= variable + '1';
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Seriously, I don't understand what you are talking about. The "classic variable = variable + 1" consumes exactly 4 MAX 3000 macrocells for a 4-bit counter, as expectable. You can use the Quartus binary counter template as reference, as suggested. Hopefully, your code can keep up. I couldn't check it, because I miss your halfAdder component.
Particularly the 16% number sounds dubious. What are you comparing with?
P.S.: Assuming your code is calculating correctly (your first one didn't, as I showed), it's still consuming extra resources, because it's double registering the result. That's something, the compiler can't optimize away, because it thinks you mean it. So it surely won't achieve the 4 macrocells reference.
P.P.S.: Of course, you are able to achieve the minimal implementation also using halfadders, or whatever style you prefer, respectively are required to. But the sequential code must create only a single level of registers, one for each counter bit. The design compiler should be clever enough to minimize the combinational part (the adder logic) to the basic arithmetic operation.
One more supplement: I erroneously stated, that the result is double registered. But you are consuming additional resources by decoding an unsuitable range for the clkdiv output. As long as you don't require aparticular coding, you can simply output the counter MSB, which returns to the minimal 4 macrocell solution.
It's also interesting to see, how a counter is implemented in a MAX3000 CPLD. Even though you can suggest adders with carry, the compiler won't use it. At least up to a 32 bit counter, it uses a huge logic term combining all DFF outputs. If you consult the MAX3000 hardware handbook, you'll understand why. Of course it's completely different when synthesizing FPGA hardware.
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