Optimum way to do Count = Count + 1 Using only std_logic_1164

Hello everyone, thanks for your replies.

As std_match mentioned I only used half adders modules. I tested my counter making a clk division and running on modelsim.

The code is next

library ieee;

use ieee.std_logic_1164.all;

entity clkdiv is

port(

sysclk : in std_logic;

sysrst : in std_logic;

clkdiv : out std_logic

);

end entity;

architecture arch of clkdiv is

component halfAdder is

port(

ah : in std_logic;

bh : in std_logic;

sh : out std_logic;

ch : out std_logic;

);

end component;

signal cnt : std_logic_vector(3 downto 0);

signal cn1 : std_logic_vector(3 downto 0);

signal carr : std_logic_vector(3 downto 1);

signal tmp : std_logic;

[/INDENT]begin

h0: halfAdder port map(cnt(0), '1', cn1(0), carr(1));

h1: halfAdder port map(cnt(1), carr(1), cn1(1), carr(2));

h2: halfAdder port map(cnt(2), carr(2), cn1(2), carr(3));

cn1(3) <= cnt(3) xor carr(3);

process(sysclk, sysrst)

constant clow : std_logic_vector(3 downto 0) := x"7";

constant chigh : std_logic_vector(3 downto 0) := x"F";

begin

if sysrst = '0' then

cnt <= x"0";

elsif sysclk = '1' and sysclk'event then

cnt <= cn1;

if cnt < clow then

tmp <= '0';

elsif cnt >= clow and cnt < chigh then

tmp <= '1';

else

cnt <= x"0";

end if;

end if;

clkdiv <= tmp;

[/INDENT]end process;

[/INDENT]end architecture;

Maybe it can be improved, but at least I can make it fit in the CPLD since a reduction of ~16% than using the classic "variable <= variable + '1';

Thanks all you guys,