OpenCores CAN

I tried also to use the opencore can recently and following issues appeared :

- the fifo's were not working, and because of some compiler warnings about the incompatibility of the memory, I got rid of them. You don't really need a receive fifo with a nios processor. A CAN message itself is around 100 to a few 100 microseconds, so if you can't read the message during this time, the whole system must be changed anyway.

Without the fifo's it saves you also a few 100 logic elements. (the core dropped from around 1400 to 1100 cells).

A receive fifo is impemented in our software and is filled from interrupt, this fifo existed also with using the SJA1000 chip, a fifo on a fifo should be a bit stupid.

- the most of the time for reading or sending a message to the can core is shifting data around for the CAN-ID's. They are placed in an unnatural way into the register space of the SJA1000 component (the 'prototype' of the core). Restructering them gives less instructions in interrupt.

- why not using a 32 bit interface?? It is a 32bit processor and all the signals stay inside the chip anyway. For example with a 32 bit interface, checking how much 'bytes' to send to the core will take longer than just dumping two DWORDs (8 bytes is the maximum) to the correct address.

-without the fifo's and a little bit more fiddling with the core, it's easy to get rid of the extra wait state in the bus interface also.

Interrupt time for sending and receiving dropped from around 10µs to around 3µs doing the things above.

Just some ideas,

Stefaan