Forum Discussion
Honored ContributorOn/Off led
unable to turn on/off led. the component does not trigger does anyone knows why?
--main filearchitecture Behavioral of DigitaleKlok is
component OnOff is
port (
led_state : in std_logic_vector(1 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end component ;
signal sig : std_logic_vector(1 downto 0); --> 01,10,11
begin
process(Clock)
begin
if (SW(2) = '1') then
sig <="01";
else
sig <="10";
end if;
end process;
test: OnOff port map (sig);
end Behavioral;
------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity OnOff is
port (
led_state : in std_logic_vector(1 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end entity OnOff;
architecture Behavioral of OnOff is
begin
process(led_state)
begin
if(Clock'event and Clock='1') then
if (led_state = "10") then
LEDR(9) <= '1';
end if;
if (led_state = "01") then
LEDR(9) <= '0';
end if;
end if;
end process;
end Behavioral;7 Replies
Altera_ForumTrue, but my point still stands. With the process sensitive to clock the similation will look like it's triggering on both clock edges, but on the real hardware its totally asynchronous.
- Altera_Forum
That is true Tricky. For issues like LEDs and human-finger triggered switches and similar starters' projects, I don't see any need for clock edge to sample changes. However it is useful to use correct methods at least to keep the professor happy.
Apart from that I might also use a slow clock to debounce the tremor of old fat fingers. The benefit of not using clock is that you don't need to care about the fuss of TimeQuest reporting failures on registers. - Altera_Forum
is the test a testbench or a synthesisable file? either way, you're not using the correct synchronous template for the process. You have clock in the sensitivity list but you're not using it in the process. This will lead to simulation/synthesis missmatch.
- Altera_Forum
I have figured out what went wrong.
My code works ok i was changing the the wrong switch. SW1 instate of SW2 Thank you Kaz. - Altera_Forum
Since your code is not complete, it is hard to tell about signals like hour/minute counters.
For now I suggest changing the if construct of component LED to: if led_state = "01" then .... elsif led_state = "10" then ... end if; Make sure you are not switching LEDs too fast to be visible. - Altera_Forum
I think I have corrected the portmap, but still nothing happens when I change the switch state.
-- main file port ( Dselect : in std_logic; -- 24000000HZ SW : in std_logic_vector(3 downto 0); KEY : in std_logic_vector(3 downto 0); LEDR : out std_logic_vector(9 downto 0); HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(0 to 6) --> Display_select ); architecture Behavioral of test is component leds is port ( led_state : in std_logic_vector(1 downto 0); LEDR : out std_logic_vector(9 downto 0) ); end component ; signal Alarm_state : std_logic_vector(1 downto 0); --> 01,10,11 begin process(Clock) begin if (SW(2) = '1') then if (hour = alarm_hour) then if (minute = alarm_minute) then alarm <= 1; end if; Alarm_state <="01"; else Alarm_state <="10"; alarm <= 0; end if; end process; test: leds port map (Alarm_state, LEDR); end Behavioral; -- library IEEE; use IEEE.std_logic_1164.all; entity Leds is port ( led_state : in std_logic_vector(1 downto 0); LEDR : out std_logic_vector(9 downto 0) ); end entity Leds; architecture Behavioral of Leds is begin process(led_state) begin if(Clock'event and Clock='1') then if (led_state = "10") then LEDR(9) <= '1'; end if; if (led_state = "01") then LEDR(9) <= '0'; end if; end if; end process; end Behavioral; - Altera_Forum
The first thing to do is portmap correctly for both input and output of OnOff
