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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP

Hello Intel forums, I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround des...
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Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi,

Please help me understand few things.

1) Are you checking the PLL status in HW or in simulation?

2) In the port map, the 'locked' signal is open. How are you checking the status of the PLL.

3) What is the status of rst input port to the PLL?


The frequency of the output clock from PLL is valid only after it gets locked. You should be measuring it only after lock.

Regards


  • SDe_J's avatar
    SDe_J
    Icon for Occasional Contributor rankOccasional Contributor
    3 months ago

    Hi,

    Thanks for your response. Here's my answer:

    1. I am checking in HW

    2. I use signaltap to monitor the port directly

    3. 'rst' is low when I check the locked status.

    Regards,
    Sam