One simple issue about I/O input and output

Yes, the Cyclone 10 GX FPGA fabric can absolutely receive that single-ended MCU signal and re-drive it out as a true LVDS differential pair to your pulse distributor. This is a standard signal-bridging use case with no architectural obstacles.
Here is how it works end to end:
Single-ended input side
The LVDS I/O banks support differential and single-ended I/O standards up to 1.8 V. 5.1. I/O and Differential I/O Buffers in Cyclone® 10 GX Devices — Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook So your MCU's single-ended signal can land on an LVDS I/O bank pin, provided its voltage is within that 1.8 V envelope. If the MCU drives a higher voltage (e.g. 3.3 V or 2.5 V), you must route it to the 3 V I/O bank instead — the 3 V I/O bank supports only single-ended I/O standards up to 3 V. Selectable I/O Standards and Flexible I/O Banks Either way, the FPGA fabric receives a clean logic signal.
Fabric forwarding
Once inside the fabric, the signal is just a logic net. You can connect it directly — or through any combinatorial/registered path — to the LVDS transmitter output instance. No special IP is required for a simple forward path.
LVDS output side
The LVDS I/O pins form pairs of true differential LVDS channels, and you can use each LVDS channel as transmitter only or receiver only. 5.1. I/O and Differential I/O Buffers in Cyclone® 10 GX Devices — Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook All I/O banks have dedicated circuitry to support the true LVDS, RSDS, and mini-LVDS I/O standards by using true LVDS output buffers without resistor networks. 5.5.5.2.2. LVDS, RSDS, and Mini-LVDS Termination — Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook This means no external resistor ladder is needed to form the differential pair — the on-chip LVDS output buffer drives the pulse distributor's LVDS input directly.
LVDS speeds are supported up to 1.434 Gbps, and each LVDS pair of pins has differential input and output buffers, allowing you to configure the LVDS direction for each pair. FPGA General Purpose I/O — Cyclone 10 GX Device Overview
Practical notes
- Assign the LVDS output standard to the positive pin of the chosen pair in the Quartus Prime Pin Planner; define just one pin to represent a differential pair and make a pin assignment for the positive end of the pair — when you specify a differential I/O standard, the Quartus Prime software automatically places the corresponding negative pin. I/O Signaling Type
- Keep the LVDS transmitter pair within a single LVDS I/O bank. For an LVDS SERDES IP transmitter interface contained within a single I/O bank, drive the transmitter using the PLL in the same I/O bank 5.6.6.6. Guideline: Pin Placement for Differential Channels — Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook (relevant if you use the SERDES path; for a simple single-bit forwarding path without SERDES, PLL involvement is not mandatory).
- Note that assigning LVDS I/O to the 3 V I/O bank will cause a fitter error — the LVDS I/O standard is not supported in 3 V I/O banks. Error (175020): The Fitter cannot place logic pin in region (x, y) to (x, z), to which it is constrained, because there are no valid locations in the region for logic of this type. Ensure the LVDS output pair is on an LVDS I/O bank.
In summary: receive the MCU signal on a single-ended I/O pin, forward it through the fabric, and assign the destination pin pair as LVDS output — the Cyclone 10 GX true LVDS output buffer will drive your pulse distributor's LVDS input directly.

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