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Altera_Forum
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Honored ContributorOne Line 10K LE ???
hello, I am writing Cyclon III application and came to this strange thing, the falloing lines take 10K LE from the FPGA. i cant tell why, its not that commplicated to calculate...
The rebellious line: else if ((LastPoint < YPixel && Plot[XPixel] > YPixel) || (LastPoint > YPixel && Plot[XPixel] < YPixel)) ..... LastPoint ,YPixel and all other vars are 10bits... (this line is just connecting dots in graph)4 Replies
Altera_ForumHow big is XPixel, or more specifically, how big is Plot? If you're expecting this to be a memory and you're reading 10 bits, it's probably being put into FFs with a large mux. Just a guess though.
- Altera_Forum
Please show the complete code definition. The explanation is far from being clear.
- Altera_Forum--- Quote Start --- Not complicated, but the condition has to be checked for each array element of the array Plot individually. --- Quote End --- why do you say for each element? LastPoint, YPixel and Plot[XPixel] are all 10x1bit elements and not arrays and XPixel is integer that incremented each clock
- Altera_Forum
Not complicated, but the condition has to be checked for each array element of the array Plot individually.
