On-Chip termination in Cyclone IV FPGA to interface it with the SDRAM

Hi All,

I am dealing with the pin assignments specifications for Altera's Cyclone IV FPGA.

I am using Altera's Quartus II software and using its QSYS tool I have designed a system

to interface DDR2 SDRAM with FPGA. While I was assigning pin assignments to

FPGA. I came across the feature - on-chip termination, which fascinated me as it

can deduct the requirement of adding pull-up resistors and can reduce the bulkiness of the

board.

As all the pins from FPGA to SDRAM are output or bi-directional, I have applied

output termination with series 50 ohms with calibration to all the pins. My questions are-

1.is my decision of applying output termination, with series 50 ohms calibration,

to bi-directional pins correct?

(I have read that

For input pins, input termination should be used with parallel resistors

For output pins output termination should be used with series resistors

For bi-directional both the input and output termination or dynamic

termination should be used.

But in Cyclone IV input termination and dynamic termination options are not

available. These options are there in Stratix family FPGAs)

2. If output termination with series 5o ohm with calibration is correct, do i need

to add any external resistors for termination on fpga side?(Except RUP and RDN

resistors)

Please don't misguide me if you are not sure about your answer. It may cause a very big trouble to my PCB department. It's better that you give some references so that I can clear some things in my mind about OCT. Thank you.

Ashish Devre