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Altera_Forum
Honored Contributor
Honored ContributorOdd Counter Output.
Hello all; I am trying to learn AHDL and have run into a problem. I tried searching the forum, but could not find anything like what I am seeing. I am sure I have done something to the se...
Altera_ForumHonored Contributor
Honored ContributorTo Larry: your counter works fine, but you have the wrong order in your simulation showing Q[0..3] rather than Q[3..0].
To Tricky: to a (self-)starter AHDL is much more intuitive then VHDL or Verilog. But is less high-level than the other 2, so nplttr's recommendation certainly is good advice.
