Number of gates ?

Thanks for your suggestion. I preferred a FPGA that have more I/O. You have your point there sir. Thank you.

I would go with the cyclone 4 - the cyclone is an older part not supported by the web edition any more, and has no built in multipliers.

There are a few cores available on Opencores:

Thanks for your replied sir.

You dont really need a higher end chip unless you need lots of clocks, IOs or lots of high speed (in the 5+Gbps range) intefaces.

You could probably use a cyclone without a problem.

Thanks all for helping me. Im new to this FPGA, i would like to implement AES on FPGA. Is it a specific FPGA that i must use or i can choose any FPGA to do this?

Before Cyclone family, Altera used to specify FPGA resources as "typical gates" and put this number into the device name. According to this calculation, a 4-LUT LE counts as 20 "typical gates". See ACEX family data sheet for details.

It is difficult to predict how many LUTs any given implementation will use. The best option is to write your AES code, synthesize it in Quartus and check the reports to see how many LUTs and RAM modules are used.

Let's say if i would like to implement an AES on my FPGA, is it important to know the number of gates?