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Honored ContributorNumber of gates ?
Hi all.
From the datasheet i got from internet for FPGA Cyclone IV (EP4CE6E22I7N) do not mention the number of gates. What does its means? If compared with flex 6000 family(EPF6016TI144-3), its do mentioned the number of gates but not the total RAM bits. It's like vice versa between the two FPGA. Can someone explains it to me please. Is it related between number of gates with total number of RAM? p/s : Attached is a comparaison i made between 3 FPGA (i need to replace the left one) Thanks and Regards13 Replies
Altera_ForumFPGAs for a long time have used multiple input LUTs. Each LUT can be configured to contain between one and several "gates", so the total gate count is pretty meaningless.
- Altera_Forum
Hi and thanks for your answer.
Does it means there is no limitation for the number of gates? or how does it go? How about the total RAM bits? is it reflected with the number of gates? Thanks and regards - Altera_Forum
It is not unlimited, but different designs may have different "max gates" just by the way they are designed. The important figure is the LUT usage.
For RAM - FPGAs have built in rams that are separate from the LUTs. but they can also be configered to use LUTs as ram. Total memory bits also includes max LUT ram uage IIRC. But its not as simple as total bits, as usage can be affected by how efficiently you use the rams in your design. A more sensible question to ask would be what your project is? often it is the IOs needed, memory requirements or built in multiplier requirements that drive the FPGA choice rather than LUT usage (as the others are a lot easier to calculate before you implement your design). - Altera_Forum
Let's say if i would like to implement an AES on my FPGA, is it important to know the number of gates?
Thanks and regards - Altera_Forum
It is difficult to predict how many LUTs any given implementation will use. The best option is to write your AES code, synthesize it in Quartus and check the reports to see how many LUTs and RAM modules are used.
- Altera_Forum
Before Cyclone family, Altera used to specify FPGA resources as "typical gates" and put this number into the device name. According to this calculation, a 4-LUT LE counts as 20 "typical gates". See ACEX family data sheet for details.
- Altera_Forum
Thanks all for helping me. Im new to this FPGA, i would like to implement AES on FPGA. Is it a specific FPGA that i must use or i can choose any FPGA to do this?
Thanks and Regards - Altera_Forum
You could probably use a cyclone without a problem.
- Altera_Forum
You dont really need a higher end chip unless you need lots of clocks, IOs or lots of high speed (in the 5+Gbps range) intefaces.
- Altera_Forum
Thanks for your replied sir.
Maybe im going with FPGA EP4CE6E22I7N (Cyclone IV) or EP1C3T144I7N (Cyclone). Do you know where can i find a documentation for how to implement an AES on FPGA or maybe a AES core for FPGA? Thanks and Regards
