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Altera_Forum
Honored Contributor
Honored ContributornStatus can't go high
I have just finished my pcb of EP3C25F324, but it can't work
when I power on the board, all user IO pins stayed high, the nSTATUS remaid low, and nCONFIG statyed high. Is't the problem of POR? Or the power of VCCA,VCCINT,VCCIO have some problem? I used the JTAG an AS config way via the Figure 10-30 on cyclone3 device handbook,following is my scheme,and I connect VCCIO1 to the VCC3.3,and the others to the VCC2.5. http://1824.img.pp.sohu.com.cn/images/2009/6/17/9/26/122983f4b5dg214.jpg15 Replies
Altera_ForumSince nSTATUS is stuck low it sounds like it could be a POR problem. Though I don't know of a POR problem with this specific device for Altera. But there are other reasons a device may not exit POR too, like voltage levels on supplies all must be above the POR trip points, control pins need to be tied or driven correctly, etc...
Debug techniques: I would put a scope on nSTATUS and trigger on a rising edge, single sequence (Single event trigger, one time trigger). Try varying trigger point voltage levels. Around 0.2 to 0.8V and look for a rising pulse then nSTATUS should drive low when entering POR, but should also release nSTATUS back high again after POR. Also list for us your voltage supplies and what they are powered to. Especially VCCIO of the banks that have configuration pins in them. I noticed the JTAG header is powered at 2.5V, the EPC is powered at 3.3V, what are the voltages of VCCIO for these banks?- Altera_Forum
It's scheme of power, is this enough?
http://1834.img.pp.sohu.com.cn/images/2009/6/17/14/0/122995e0772g215.jpg - Altera_Forum
Can you list what all of your voltage rails are connected to including VCCINT?
Jake - Altera_Forum
thanks for your reply!
I can't program anything via JTAG,when I config the FPGA ,the quartus programmer said:can't access the JTAG(I use usb blaster). - Altera_Forum
So are you able to program something into the EPCS flash? Are you able to program the part via JTAG?
Jake
