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Honored Contributor
Honored ContributorNot operational : clock skew > data delay
I'm currrently doing a project on emulating a CPU functions. i've integrated various blocks of the CPU and during the compilation I received this warning: Warning: Circuit may not operate. De...
Altera_ForumHonored Contributor
Honored Contributorkaz,
what do you mean by gated clock? i'm using if clk'event and clk= '1' then... to detect the clock signal. in each clock signal will transit to another new state. furthermore, what is global lines? i'm sorry i'm really i newbie in vhdl
