not continuous readdata from ddr2 in burst mode problem

hi,

in my sopc ，system clk is 100M ,and ddr clk is 150M in half rate , there is several master to access ddr, and add pipeline bridge and clock crossing bridge .

i read ddr in burst mode ,and burst length is 0xe, by signaltap readdata is not continuous ,and from the first data to the last data cost 37 clkcycle . why not

continuous?

here is my signaltap and sopc