"No CFI table found"

I did this.

Reset vector to the flash memory and exception vector to an volatile memory but I have already the same problem.

However the example project it's all right. But the toplevel of the Nios was created in verilog (I only known the vhdl) and it's an advanced project so I can't modify it.

I try to create a new project who is a copy of the example project with only I need. But I have the problem with the CFI table.

Do you know if there is an option for changing verilog in vhdl ?

Do you know a good translator (free software) : verilog -> vhdl ?

So, I could use the example project and modify it.