Forum Discussion
Altera_Forum
Honored Contributor
17 years agoCertainly, you will get errors as you have overlooked so many clock-crossing bridges! Possibly you need to re-connect 'tse_ssram_clock_bridge' to 'flash_ssram_pipeline_bridge'. After doing that mentioned error would be reduced but you will have other address alignment errors as I can see many clock-crossing bridges in your design. I suggest you to start from scratch add component one by one and see how things moving.