Forum Discussion
Altera_Forum
Honored Contributor
11 years agoJust an update. I have a couple of running theories, if anyone could rule any out that would be great. I've been studying a reference design (http://www.alterawiki.com/wiki/reference_design_-_cyclone_v_hard_memory_controller_with_avalon_mm_data_width_expanded_for_user_ecc) and cannot see anything I have set up differently.
1. The MPFE will not work as the program store for the NIOS 2. The MPFE does not support bursting (Currently set to 64 bursts, though have tried disabling bursting) 3. The MPFE does not work with bidirectional ports (Have tried second (non NIOS) ports as in reference design to read and write but to no avail) 4. Due to the way the mSGDMA works, it never stops writing/reading to surrender control to the NIOS. I have edited it to continuously loop back on its descriptors so the chain never ends. I've tried to rule out 1 - 3 already, but am running out of ideas.