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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

NIOS-II "Memory Test" strange behaviour

Hi, I have a Cyclone V based product (not a dev-kit!) with 512Mb of SDR SDRAM attached to the FPGA for use by the NIOS-II processor. This is 32-bit wide memory. To test the attached memory ch...
sirujjan's avatar
sirujjan
Icon for New Contributor rankNew Contributor
1 year ago

Hello dear

Please can you update if your issue was resolved??
My design testing in eclipse is suffering the same issue exactly. Because my DE board has 1GB SDRAM, so its address range is: 0x4000_0000 - 0x7fff_ffff. But I am unable to fully test it.

Secondly, my DE board consists of another SDRAM (2 separate modules of 1GB each). This second SDRAM addressing in qsys is: 0x0000_0000 - 0x7fff_ffff. I am unable to test this second SDRAM at all.

Please can you help me update about your issue if resolved already?