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Altera_Forum
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17 years ago

Nios II CPU and Firmware access Problem

About the application: We have a multichannel application. Each channel design is based on a Altera Cyclone FPGA, which includes an internal NIOS II processor and an external program 32bit ASRAM (asy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

you could change the waitstates on the asram component. You would add a cycle of latency to the asram interface, but that could be compensated for perhaps by increasing the cache?

--dalon