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Altera_Forum
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18 years ago

Nios II CPU and Firmware access Problem

About the application: We have a multichannel application. Each channel design is based on a Altera Cyclone FPGA, which includes an internal NIOS II processor and an external program 32bit ASRAM (asy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

This was a similar posting albeit about SDRAM. I reckon a lot of the comments are relevant though.

The Fast Output Enable Register option would probably help you here too. Apply this to the address and control pins (Only works if they are driven direct from a register). Hopefully this would reduce the control and address latency to the RAM