Forum Discussion
Altera_Forum
Honored Contributor
8 years agoI recommend leaving the Nios and DMA cores on their own clock domain and just have the data cross clock domains using a FIFO (search for "FIFO" in Qsys and you'll find a couple of them). So you would push the pixels into the FIFO at 24MHz and then have the DMA empty the FIFO at a much higher speed. Make sure to make the FIFO depth large so that you can handle gaps between frames without underflowing.