Altera_Forum
Honored Contributor
17 years agoNIOS Custom instruction compilation problem
Hi everybody,
I'm trying to add a custom instruction to a NIOS processor, through the SOPC Builder tool, with tools version 8.1. When I try to generate the system (button "generate" in SOPC Builder), I get the error : Error (10867): Verilog HDL or VHDL XML Interface Error ... : port "nY1" has an unsupported type The mentioned code line is : entity fp_exp_exp_y1 is generic ( wF : positive := 23 ); port ( nY1 : in std_logic_vector(fp_exp_wy1(wF)-1 downto 0); nExpY1 : out std_logic_vector(wF+fp_exp_g(wF)-1 downto 0) ); end entity; This entity is part of the custom instruction, and uses the VHDL function 'fp_exp_wy1', which seems to be the problem. The same error is reported for output port nExpY1, unless I remove the use of the 'fp_exp_g' function. If I try to compile the VHDL block of the custom instruction in a separate Quartus Project, it compiles and synthesize without problem. If I remove the function call (using only constants in my input signal definition), it works fine. I think the code used to work fine with a previous version of Quartus, but downgrading the tools isn't convenient. And in a general way, the SOPC tool complains about problems when importing VHDL modules, while they compile with no error in Quartus. Is there a way to make SOPC Builder accept my VHDL code ? Thanks.