Sorry, I don't know the answer to that particular question as I do not use the NIOS software tools.
Bring up Qsys and see what the IRQ number for the SPI core is, check that you're using the right IRQ line.
If I was faced with this issue, I would create a Modelsim testbench and generate an SPI transaction, and then trace the IRQ line from the component to the NIOS IRQ lines to confirm that the SPI slave core was doing what it is supposed to.
Alternatively, you can do the same in hardware using the SignalTap II logic analyzer. Probe the SPI core IRQ line and see if it asserts properly.
I have not looked at the SPI core registers, but there might be an interrupt enable line both at the peripheral and at the processor that you need to enable. Check the documentation.
You're definitely on the right track though.
Cheers,
Dave