Can you be a little more specific in your definition of what you want regarding master and slave.
The NIOS II is a processor, and it is a master on the Avalon-MM bus.
The NIOS II can have an SPI peripheral in its memory map. That peripheral will be an Avalon-MM slave. The peripheral could be an SPI master or slave, depending on the implementation.
There is also an SPI-to-Avalon-MM bridge that you can use to have an SPI slave that allows you to control an Avalon bus as a master.
Confusing, eh!
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I want to implement a nios 2 softcore with an spi slave
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I suspect that what you want is an Avalon component that implements an SPI slave. That component would also be an Avalon-MM slave. Take a look in the Embedded IP Peripherals users guide.
http://www.altera.com/literature/ug/ug_embedded_ip.pdf p85: "The SPI core can implement either the master or slave protocol".
Cheers,
Dave