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drecassiano's avatar
drecassiano
Icon for New Contributor rankNew Contributor
3 years ago

NIOS 2 Development: Compile

I create a NIOS 2 processor in platform designer 18.1 and then transferred into a Verilog file and then I do the following below in Quartus prime lite edition18.1. (double click) core(dir) (sel...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Below are the instantiations of core u3 in DE10_LITE_Golden_Top.v :

.altpll_0_c1_c1k ( ),

.altpll_1_areset_conduit_export (ARDUINO_IO[2]),

.altpll_1_locked_conduit_export (ARDUINO_IO[3])


As sstrell mentioned earlier, this is interconnection problem. I don't see ports above altpll_0_c1_c1k, altpll_1_areset_conduit_export and altpll_1_locked_conduit_export being instantiated in core.v as well as core_inst.v. May be you have to check again. There is no error at altpll_0_c1_c1k because it is not being connected yet.


Thanks,

Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.