Nichestack Tutorial Using Arria V GX starter board

Hi all,

Has anyone tried/succeeded in completing the nichestack tutorial provided on Altera's website using the Arria V GX starter board?

I have been working at it for a couple weeks now, and have been running into problems downloading the ELF file to the board. I have been receiving errors such as "Downloading ELF process failed" and "assertion "m_state==STATE_DEBUG" failed."

Also, more recently (after starting over from scratch and following the Cyclone V, I am getting run configuration errors that the system id and timestamp not found on target at expected base address)

Basically what I have been doing is trying to replicate the format of the cyclone V ethernet system also provided on altera's website (They have 2 different Cyclone III ethernet systems, as well as Cyclone V and Stratix IV ethernet systems provided). I have been using the cyclone V since it uses the same ethernet interface as the Arria V GX starter kit (10/100/1000Mb Ethernet MAC, with the RGMII setting). I have modified some of the components, such as clocks, memory and flash to accommodate settings such as address size and data size. I have also adjusted the pin planner to match the Arria V's pin layout. I have kept the verilog file the same, as it just connects the ports of the qsys system to the actual board pins. I have also used the cyclone III 3C120 C files provided in the nichestack tutorial files (since it uses RGMII). My program compiles in Quartus II 12.1 SP 1, and also builds fine in Nios II SBT, generating a .elf file. However, after run as -> nios II hardware, I find that the run configuration pops up and tells me the system ID hash and timestamp not found on target at expected base address.

I was wondering if there was anyone out there who was able to complete this tutorial using the Arria V, and if so if you could give me some insight on how you were able to complete it. Thank you all for your time.