newbie question on FPGA/CPLD's

To answer the second question first, yes it's ns scale, comparable with e.g. HC or AHC logic. Consult the datasheet or perform a Quartus timing simulation to see the exact logic delays.

Clocked logic behaves similar as if built from discrete flip-flop logic devices. As far as the logic response has to travel one ore more flip-flop stages, it will be of course slowed-down with a slower clock. That's usually, what a clocked logic would be expected. You always get exactly the programmed behaviour, also in terms of clock cycles.