Honored Contributor
Honored ContributorHi Manos:
The Cyclone V series has the SE, SX and ST flavors that have dual ARM A9 hard cores already built in. So you get a higher performance CPU already in the FPGA, with out using any additional fabric. (It also has hard memory controllers, and PCI controllers depending on the exact device).. For a performance SOC design, this is the way to go, because you get the performance of a A9 with no LE requirements. This allows you to use all of your LE's for your non CPU pieces. At 250 Msps, in Cyclone III/IV, you will probably be fighting timing issues.. That's pushing the performance of these families. I currently have a design running in Cyclone II at 102.4 Msps (barely). We just recently moved to Cyclone V. There was a push to move to 204.8 Msps, but we advised against it even in Cyclone V. There requirements didn't merit the 200+ Msps, and it was just additional pain, for no appreciable gain. They had multiple display requirements, as will as a high update rate requirement, We ended up going with a IMX6 + Cyclone V E family combination. The SE family wasn't out at the time, so it wasn't a contender, but even if it was, we probably would have still gone with the IMX6, because of the 3 displays. Everything is always a trade off. I haven't worked with your particular touch panel, but in general your block diagram will work. The questions comes in will it be enough. The CPU still has to read every sample and send it to the LCD, if you can write the LCD frame buffer directly from hardware, that will give you much better performance. But it will also be much more difficult to implement. Regards, Pete
