Honored Contributor
Honored ContributorHi Pete,
Thanks so much for your time to answer to my post. The way i see it is that using a Nios II configured FPGA is an all-in-one solution because this will save some money and time as well design effort integrating an additional ARM uC. You told me that a Nios processor would not write fast enough to the memory to keep up with the 250Msps expectations of mine. In fact, i do not expect the cpu to perform anywhere near that. What i was thinking was implementing, in the FPGA, a direct ADC to Memory controller with near-full and/or full flags so that in some way the capturing will stop on even a custom level of the memory completeness. After that, the Nios cpu will process the data by having access to the memory via another CPU to RAM controller. In this way the cpu will not have to strungle or bother with the capturing process. After the Nios cpu processes data captured and updates the LCD with the new data cycle, it will trigger a new capture by accessing the first FPGA controller (ADC to Memory). Talking about LCD update, i was thinking that i want to keep a high rate of display update, regarding the waveform, over 15-20 FPS mostly at high frequency content as measuring 50Hz with a 20FPS rate is not possible by nature. That is why i purchased a RA8875 based LCD (http://www.buydisplay.com/default/5-800x480-tft-lcd-module-touch-display-w-controller-i2c-serial-spi.html) that has amazing (supposingly) specs like drawing lines and other shapes just by passing the coordinates of your choice to it and it then uses no cpu to draw the line as well as doing other stuff with no cpu overhead. Please see the attached block diagram and kindly comment on whether my thinking is anywhere near a doable implementation inside the FPGA. Awaiting your comments. Regards Manos
