Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Newbie Help Request CPLD MAXII

Hi all. I want to build a digital clock, with several 7 segments displays (HH:mm:ss). How can i make the 1s clock to drive my 4bits counters? My board has a 50Mhz clock. How can i make 1s pre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Anyway, you could write your own divider by 50,000,000 as an exercise. Try to write it in Verilog to start with an HDL language. The frequency accuracy in ppm will be the same as the one guaranteed by your crystal oscillator.

You can use the Quartus II templates to start learning.

Once you have created your .v file go to

Edit>Insert Template and browse the available templates.

Cheers

OD