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Altera_Forum
Honored Contributor
Honored ContributorNewbie Help Request CPLD MAXII
Hi all. I want to build a digital clock, with several 7 segments displays (HH:mm:ss). How can i make the 1s clock to drive my 4bits counters? My board has a 50Mhz clock. How can i make 1s pre...
Altera_ForumHonored Contributor
Honored ContributorWell don't start by asking what the best language is (because everybody knows it's Verilog). No really you may start a battle. If you want your skills to be broadly useful than chosse Verilog or VHDL.
Well now ... 50MHz = 50,000,000 clocks per second. So technically all you have to do is write a counter that counts to 50,000,000 and that equals one second. In reality however, the accuracy of this calculation depends entirely on the accuracy of the crystal producing the 50MHz clock. Crystals come with specified tolerances. When someone designs a product that requires extremely accurate timing, they choose a low frequency crystal with a tight tolerance. So in reality you'd like to have a crystal in the low kHz range with an extremely tight tolerance. Jake
