Newbie - Where to put my Time/Energy

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The data will be IQ data from an RF front end and I am not sure what processing will be required. The ADCs will run between 15-20 MSPS.

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This is quite 'slow' compared to what FPGAs can achieve. If you need multiple ADCs, with lots of bits, then you might want to consider using a JEDEC JESD204 ADC (NXP and TI have them). They multiplex the outputs onto LVDS or SERDES signals. You need a higher I/O rate FPGA, but you have less board routing and signal switching issues. The DE0 can be used for parallel output devices to start with.

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This is good to know. I think I will try to get the UART working first without the NIOS uC. How would reccommend proceeding? SOPC tool to try to incorporate the UART with the JTAG-to-Avalon-MM bridge? Does that even make sense?

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The components will both use the JTAG interface. I have not used the JTAG-UART, but you'd talk to that with the nios2-terminal program. The Avalon-MM master would be communicated with using SystemConsole. The Altera tools are bad when it comes to 'sharing' the JTAG interface, so you might run into issues. I'd say go for it ... if you have trouble, come back here and complain, and we can see what to try next.

Alternatively, you can talk to an FTDI UART (or another USB-to-Serial device, with the RS232 translators removed) via the DE0 I/O pins, and use the Avalon-MM master to talk to that. The FTDI FT245 module is about $20 on Digikey. That has a parallel output to the FPGA, but its pretty simple to interface to.

Cheers,

Dave

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How fast (clock rate) and what signal processing are you doing with the data?

Dave

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That is to be determined. The data will be IQ data from an RF front end and I am not sure what processing will be required. The ADCs will run between 15-20 MSPS.

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Since you have a background in micros, this is probably a good place to start. Though you do not need to have a NIOS II processor as a master. The JTAG-to-Avalon-MM bridge allows you to read and write from an FPGA design via the USB interface.

Dave

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This is good to know. I think I will try to get the UART working first without the NIOS uC. How would reccommend proceeding? SOPC tool to try to incorporate the UART with the JTAG-to-Avalon-MM bridge? Does that even make sense?

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Learn how to use Modelsim, and learn how to write testbenches.

You should use Modelsim and a testbench to check that each of the components you design work, and then integrate them into a larger system and check that they work there. The Avalon master can be your NIOS core, or it can be the Avalon-MM BFM (bus functional model - a simulation only component).

Dave

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OK, I have work to do. I am flying solo on this project and it is way overwhelming.

Thank you!

Rich

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If you get stuck, just ask questions.

Cheers,

Dave

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The application will be reading parallel output from a couple of high speed ADCs and processing that data into a serial stream.

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How fast (clock rate) and what signal processing are you doing with the data?

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I would like to start with the UART. I believe that I will require the NIOS processor to do computational manipulation of the data.

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Since you have a background in micros, this is probably a good place to start. Though you do not need to have a NIOS II processor as a master. The JTAG-to-Avalon-MM bridge allows you to read and write from an FPGA design via the USB interface.

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There are many paths that can take all my time like studying the avalon interface specifications etc. I have to be efficient with my time.

I am looking for advice on what would be a reasonable path to take to to get going to avoid heading down dead ends or "rabbit holes".

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Learn how to use Modelsim, and learn how to write testbenches.

You should use Modelsim and a testbench to check that each of the components you design work, and then integrate them into a larger system and check that they work there. The Avalon master can be your NIOS core, or it can be the Avalon-MM BFM (bus functional model - a simulation only component).

If you get stuck, just ask questions.

Cheers,

Dave