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Altera_Forum
Honored Contributor
12 years agoI found out what the problem was. Period1S was high for 1ms, so while in idle state it would send bunch of data out since Period1S = '1' would be satisfied.
I have fixed the problem with the edge detector:
library ieee;
use ieee.std_logic_1164.all;
entity edge_detector is
port (
clk_50mhz : in std_logic;
rst : in std_logic;
din : in std_logic;
change : out std_logic;
rising : out std_logic;
falling : out std_logic
);
end edge_detector;
architecture bhv of edge_detector is
signal din_delayed1 :std_logic;
begin
process(clk_50mhz)
begin
if rising_edge(clk_50mhz) then
if rst = '0' then
din_delayed1 <= '0';
else
din_delayed1 <= din;
end if;
end if;
end process;
change <= (din_delayed1 xor din); --rising or falling edge (0 -> 1 xor 1 -> 0)
rising <= ( (not din_delayed1) and din);
falling <= (din_delayed1 and (not din));
end bhv;
Now in my main code:
signal PeriodRising : STD_LOGIC;
component edge_detector is
port (
clk_50mhz : in std_logic;
rst : in std_logic;
din : in std_logic;
change : out std_logic;
rising : out std_logic;
falling : out std_logic
);
end component;
....
edetect : edge_detector port map
(
rst => reset,
clk_50mhz => clk,
din => Period1mS,
rising => PeriodRising
);
...
when idle =>
delay_next <= 0;
write_cnt_next <= 0;
if(rxf_reg = '0') then
state_next <= reading_prepare;
elsif(PeriodRising = '1') then -- Send data every 1 second
state_next <= write_prepare;
end if;