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Is this because a variable in VHDL cant store a value?
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Just so you're clear on this: Variables can store a value, and they can be used to describe a register. Remember, variables are updated immediatly and signals are updated when a process suspends. But its down to where you place the code:
--inside clocked process
count := count + 1;
if count >= 100 then
This will make count a combinitorial value, and may not store a value depending on the way its used because it is checked AFTER it has been updated.
But this will infer a register for count:
--inside clocked process
if count >= 100 then
...
count := count + 1;
Here the count value is checked before it is updated, hence the synthesisor will infer a register.
So the recommendation is you use signals until you know what you're doing with variables. Some people dont like using variables for registers because they dont use them alot and are used to the standard code structure using signals. Personally, I like to keep things in as local scope as possible, so if I have a pipeline thats only accessed in the same process, you can often do it with local variables rather than global signals.
On another note - I highly recommend you DONT generate a clock like this. Logic clocks are difficult to time, can cause glitches and are highly affected by temperature variations. I would suggest using clock enables instead.
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