Honored Contributor
Honored ContributorNo. I prefer signal, no variables, but isn't the problem. You're describing hardware with VHDL. To store a value, like a counter does, you need a register:
if ( rsr = '0' ) then cnt_reg <= ( others => '0' ); elsif ( clk'event and clk = '1' ) then cnt_reg <= cnt_next; end if; end process; this is the sequential part of the circuit. The future value stored in the register is generated by a combinational circuit: cnt_next <= cnt_reg + 1 when ( cnt_reg < 81000000 ) else ( others => '0' ); Idem with the output: process(cnt_reg) begin IF(cnt_reg = 81000000)THEN clkout <= '0'; ELSIF(cnt_reg = 27000000)THEN .... In your code you mixed sequential and combinational circuits. For good coding practices I suggest the book "RTL Hardware design with VHDL". The author is professor Pong Chu.
