New to VHDL: Understanding timer.vhd implementation

Thanks for the response. I've got a follow-up question regarding the timer.vhd implementation.

There is some code driven by an internal signal named "clk_en". At the beginning of the architecture, there's this:

clk_en <= std_logic'('1');

And then later on there's this:

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      force_reload <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        force_reload <= period_h_wr_strobe OR period_l_wr_strobe;
      end if;
    end if;
  end process;
 

What is the purpose of checking clk_en? I'm guessing it's primarily for simulation purposes as a guard in the event that there is an immediate rising edge to prevent (in this case) force_reload from being updated with data that may not yet have a defined value. Is this the case?

Thanks,

--tim