New to VHDL. Question about Wait for, After (ns) statements.

All true, but the most important thing to point out is that theese assignement are usefull only for simulation parpouse.

If you need to make a delay, your logic shall implement a counter that trig the event.

Since you told that you're a beginner, you've to understand that VHDL in all syntesis tools is a way in which you are describing something that IS BEING IMPLEMENTED.

So try to keep in mind always what are implementing how will be done in terms of flip flop and logics blocks.

Good learning :)