Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Netlist writer

Hi I am using the SOPC builder to create a NIOS based system. I wanted to use an open source tool minSSTA to perform timing analysis. The tool accepts .bench: circuit netlist file - Here is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for your quick response

I am able to generate the .vo file, does this mean that I have the license for the files.

Can I make quartus synthesize the nios2 ip to a simple library instead of fpga primitives. Or is there any eda tool which can take the output from altera synthesis and synthesize the ip into a simpler library of gates.

Are the modules provided in eda/sim_lib/stratixiii_atoms.v synthesizabe or are they just functional models which can be used in Model Sim