Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

negative sign inside FPGA

How can represent negative sign inside the FPGA ? and what is the meaning of the negative data type not synthesizable?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    What numbers are you talking about. integers are 2's compliment so effectivly has a sign bit at the MSB.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Integers are signed type; default width of 32 bits. Natural are the whole numbers are unsigned; also default width of 32 bits. If you use the numeric_std package, then you can convert between SLV, signed and unsigned to/from integer types easily. For example;

    regSLV <= std_logic_vector(to_unsigned(IntegerVariable,16));

    integerVariable <= to_integer(signed(regSLV));

    integerVariable <= to_integer(unsigned(regSLV));