need help with wake up time of cyclone II

I assume by "wake up time" you think of the time between power applied to the FPGA and the FPGA being in user I/O mode, do you?

This configuration time is described in the Cyclone II Handbook, Chapter 13; timing being dependent on the internal oscillator (with its tolerances) only (thus the 50 or 100MHz oscillator does not change anything). The configuration time also depends on the mode (AS, PS, AS(Fast) or JTAG).

(See page 18 for calculation of configuration time using AS,...)

HTH,

Carlhermann