Need Help to Verify Timing Constraints On Output Pins to External Device

I strongly believe it is possible for DDR slacks to be reported more than half period (UI) for either setup or hold and that is direct outcome of setting false paths between unrelated edges.

You should not think of DDR clock as equivalent to SDR at double rate clock in which case it is not possible. The DDR will have two registers to de-interleave data and so changes are ignored by one edge or the other.

Regarding same edge Vs opposite edge latching, you are free to try either and see which one passes. Once you choose one case then your design must be aware of it. Remember a stream of Hdata => Ldata if sampled on same edge will retain the sequence and if you decide on opposite edge transfers then the sequence becomes Ldata => Hdata and as long as you interleave/deinterleave back correctly then it should work.

If you don't set false paths on irrelevant edges then slack must be less than UI and this is unrealistically too restrictive.