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Altera_Forum
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11 years ago

Need Help to Verify Timing Constraints On Output Pins to External Device

Hi, I'm relatively new in FPGA designing, so forgive me if my question seem simple. The project I am working on involves using a Cyclone V to control 4 external DDS chips (AD9915). So I'...
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Altera_Forum
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11 years ago

Hi kaz. I couldn't do any test yesterday. But I still don't understand if it's correct to have a slack time greater than half a period in the DDR case.

I think the data valid window to sample the data should be less than half a period because if not I might be sampling data with the incorrect edge.

I will be simplifying the interface to analyze an SDR transfer case to see if and understand the results I get.

Thanks a lot.