Need Help to Verify Timing Constraints On Output Pins to External Device

To see clock skew in timequest click on report io timing and see table of values under register to output(setup, or hold).

Regarding your waveforms: it doesn't look right. For example,the same edge case should fail setup as data arrives too early and will be latched by opposite edge. It looks like the tool applies multicycle as if IF is not DDR. I am not sure why. May be you also try adjust set output delay figures instead of multicycle . If these were originally 0/0 then try -UI/+UI or even

-period/+period

which in theory is same as multicycle of 2/0 (multicycle is only known in clock period units unlike delay which is in time units).

I also assume you haven't set your PLL to any positive phase offset.

edit:

multicycle example from altera:

set_multicycle_path -setup -end 0 -rise_from [get_clocks data_clock] -rise_to [get_clocks output_clock]

looks like you can define rise_from, rise_to, fall_from, fall_to in order to apply to DDR.

In your case you just need mcp of one UI