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when FPGA clock is opposite fpga dout then tCO at fpga pins could be higher than 1 clock period. The remedy options are:
1) use PLL in compensation mode. If successful the pll will deskew clock so that it arrives at register (dout) with no delay relative to pin.
check that clock skew does get close to zero.
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I'm using a PLL in Normal compensation mode. What I understand from your answer is that if I still can't meet timing is because there is chance for the PLL to unsuccess.
In the example I've attached in the previous post, there is a "COMP" item in the clock path that I suppose is related with this. Its value is ~ -1.6ns.
Is there a way to report the skew between the input clock and the clock at output register?
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2) set setup multicycle of 2 and hold should stay as default of zero, from dout path
alternatively adjust set_output_delays by 1 clock. I believe you need to subtract one period from max but add one period to min
because addition of one clock period means advance based on altera doc.
The reason multicycle works is that we can sample correctly as long as we get same stream sequence without edge violations
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OK. This is the solution I'm trying.
I understand that I must set multicycle of 2 and this will relax timing requirements giving me an extra cycle. I've tried this and I have now two situations to consider, same edge transfers and opposite edge transfers. I think that I must set_false_path to the case I don't want to analyze, but it's confusing for me to decide which one.
If I use same edge transfers, I'm meeting timing for both setup and hold, but it's strange to me that setup slack is greater than half a period, so I will be latching in opposite edge :S
If I use opposite edge transfers, I meet timing for setup but not for hold.
I'm attaching the waveform of these two cases.
Is what I'm doing correct? Is this solution applicable when using a PLL or not using it?
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3)use manual PLL shift. This could make it difficult to manage timing figures.
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I'm not using this for now, as I understand that the PLL should ajust its phase to ease timing.
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