Need Help to Verify Timing Constraints On Output Pins to External Device

when FPGA clock is opposite fpga dout then tCO at fpga pins could be higher than 1 clock period. The remedy options are:

1) use PLL in compensation mode. If successful the pll will deskew clock so that it arrives at register (dout) with no delay relative to pin.

check that clock skew does get close to zero.

2) set setup multicycle of 2 and hold should stay as default of zero, from dout path

alternatively adjust set_output_delays by 1 clock. I believe you need to subtract one period from max but add one period to min

because addition of one clock period means advance based on altera doc.

The reason multicycle works is that we can sample correctly as long as we get same stream sequence without edge violations

3)use manual PLL shift. This could make it difficult to manage timing figures.