Need Help to Verify Timing Constraints On Output Pins to External Device

Hi all,

I'm really interested in resolving this post as I'm dealing with a very similar situation. I've just a few little differences in my case, but the heart of the problem is the same.

I'm interfacing a Cyclone V FPGA with the AD9789 DAC. From the DAC side, I have the same configuration as wzs, the DAC sends me the data clock (which is 144MHz), and expects to receive the data. One difference is that this IF is DDR, but I can ignore this for now to simplify a bit.

Then, from the FPGA side, I receive the DAC clock throught a CLK pin, pass it through a PLL with 0ns phase shift, an drive an ALTDDIO_OUT block to get the data out. I've configured the PLL to work in Normal mode and I've selected the output clk as the feedback clock to compensate for.

This is the assignment I've manually added to do this:

set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll_dac_dco:pll_dac_dco_u|pll_dac_dco_0002:pll_dac_dco_inst|altera_pll:altera_pll_i|outclk_wire[0]"

As I understand, using the ALTDDIO megafunction automatically maps the output registers to Fast registers, so from a timing point of view, I'm in the best case.

I've also defined the set_output_delay to be 0ns to simplify the things a bit, as it's the less restrictive case.

In addition, I've set false paths between the edge transactions I don't to take into account, and I've left the more restrictive cases (I think) that are opposite edge transfers. I think I can change this to same edge transfers and I will be relaxing timing a bit, but I've tried it and I couldn't meet timing anyway. I also think that it shouldn't matter too much as the data is continuosely being sent, so no matter which edge I use to send the data, there will be an edge that will sample it correctly.

When I compile the design and run timing analysis I get the same results as wzs. the total data delay through the fpga is longer than the clock period. I'm attaching the report, but it hasn't enough resolution to read it right. Anyway, the waveform view gives some idea of what I'm talking about.

I think I can't do much to get rid of this, but there is something I don't understand. Shouldn't the PLL automatically try to phase shift the output clock to meet timing? If it doesn't, how do I properly constrain the design? I think I have to use some multicycle constrain, but I'm not sure how to do that correctly.

I was thinking of opening a new post to ask my question, but then I decided that my situation has a lot of similarity with this post and it contribute to resolve the way of constraining this kind of interfaces.

Hope anyone can help :)

Diego